It's not ECC vs DDR5. There are ECC DDR5 Dimms and non ECC DDR5 Dimms. It's a bit complex because DDR5 has internal ECC, but that doesn't protect against errors on the datapath between the RAM and the memory controller (embedded into the cpu), and it doesn't have a mechanism to report errors AFAIK.
ECC without reporting puts you in a weird place where the observable error rate is less, but any observable error will be a multi-bit error. With reporting, you would likely replace a dimm that regularly has single bit errors, and your system would typically halt on any two-bit errors, and three or more bit errors may or may not be detected. Advanced operating systems may let you kill only the processes affected by the two-bit errors, but afaik that's only for mainframes and maybe commercial unix (Solaris? AIX?).
sandreas
I would recommend to read the "ECC Matters"[1] comments. All you need to know.
ECC without reporting puts you in a weird place where the observable error rate is less, but any observable error will be a multi-bit error. With reporting, you would likely replace a dimm that regularly has single bit errors, and your system would typically halt on any two-bit errors, and three or more bit errors may or may not be detected. Advanced operating systems may let you kill only the processes affected by the two-bit errors, but afaik that's only for mainframes and maybe commercial unix (Solaris? AIX?).